Ultra-large scale integrated (ULSI) semiconductor devices typically include several layers having metal wiring features (metallization layers) disposed on the top surface of the device, separated from each other in the vertical direction by insulating layers of dielectric material (interlevel dielectric layers). This arrangement of multiple wiring layers and insulating layers is required in order to provide interconnects between devices. The structure of metallization and interlevel dielectric layers is often realized using a damascene process, wherein a pattern is etched into a dielectric layer, the patterned layer is covered with metal and then polished (leaving metal embedded in the etched features), and the metallized layer is then covered with a blanket layer of dielectric material. Vertical studs (metallized vias extending through the interlevel dielectric) are used to connect one metallization level with another. As is understood in the art, the dielectric materials used are chosen for their compatibility with the etching and deposition processes involved, and to minimize the capacitance of the overall structure (that is, to minimize the dielectric constant of the material or combination of materials).
As the dimensions of ULSI devices continue to shrink, the performance of the devices is increasingly limited by the capacitance of the interlevel dielectric. For example, the capacitance of the interlevel dielectric influences the device speed (due to the RC delay in the structure of wiring and insulators), the AC power consumption of the device, and crosstalk. The capacitance of the interlevel dielectric varies in accordance with the dielectric constant of the material. In traditional semiconductor processing technology, silicon dioxide (with a dielectric constant k about 3.85) is used. In order to reduce the undesirable effects of capacitance on ULSI device performance, insulating materials with lower dielectric constants are now being used. Some examples of low-k materials are fluorinated silicon dioxide, amorphous carbon, black diamond, and some polymers. Some structures have also been developed where air gaps (having k close to 1) form part of the interlevel dielectric.
The capacitance of an interlevel dielectric layer includes not only the interlevel capacitance (that is, the capacitance between two vertically separated metallization layers) but also the intralevel line-to-line capacitance (that is, the capacitance between two laterally separated metal lines embedded in the dielectric material). As the dimensions of ULSI devices continue to scale, the aspect ratio of the metal lines continues to increase while the lateral separation between adjacent lines decreases; both of these trends lead to an increase in the intralevel capacitance. Accordingly, the intralevel line-to-line capacitance is becoming a major factor in determining the overall performance of the interconnect. It is therefore highly desirable to reduce the intralevel capacitance by introducing low-k materials into the spaces between metal lines. Most preferably, the spaces between lines would include an air gap while maintaining a physically robust structure.